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general description the max15024/max15025 single/dual, high-speed mosfet gate drivers are capable of operating at fre- quencies up to 1mhz with large capacitive loads. the max15024 includes internal source-and-sink output transistors with independent outputs allowing for control of the external mosfet? rise and fall time. the max15024 is a single gate driver capable of sinking an 8a peak current and sourcing a 4a peak current. the max15025 is a dual gate driver capable of sinking a 4a peak current and sourcing a 2a peak current. an inte- grated adjustable ldo voltage regulator provides gate- drive amplitude control and optimization. the max15024a and max15025a/c accept transistor- to-transistor (ttl) input logic levels while the max15024b and max15025b/d accept cmos-input logic levels. high sourcing/sinking peak currents, a low propagation delay, and thermally enhanced packages make the max15024/max15025 ideal for high-frequency and high-power circuits. the max15024/max15025 operate from a 4.5v to 28v supply. a separate output dri- ver supply input enhances flexibility and permits a soft- start of the power mosfets used in synchronous rectifiers. the max15024/max15025 are available in 10-pin tdfn packages and are specified over the -40? to +125? automotive temperature range. applications synchronous rectifier drivers power-supply modules switching power supply features 8a peak sink current/4a peak source current (max15024) 4a peak sink current/2a peak source current (max15025) low 16ns propagation delay 4.5 v to 28v supply voltage range on-board adjustable ldo for gate-drive amplitude control and optimization separate output driver supply independent source and sink outputs (max15024) matched delays between inverting and noninverting inputs (max15024) matched delays between channels (max15025) cmos or ttl logic-level inputs with hysteresis for noise immunity -40? to +125? operating temperature range thermal-shutdown protection 1.95w thermally enhanced tdfn power packages aec-q100 qualified max15024/max15025 single/dual, 16ns, high sink/source current gate drivers ________________________________________________________________ maxim integrated products 1 10 87 reg p_out n_out fb/set gnd in+ max15024 9 drv v cc 6 1 ep* *ep = exposed pad. 34 25 pgnd in- tdfn top view pin configurations ordering information 19-1053; rev 3; 4/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. note: all devices are specified over the -40? to +125? operating temperature range. + denotes a lead(pb)-free/rohs-compliant package. /v = denotes an automotive qualified part. * ep = exposed pad. t = tape and reel. see the selector guide at the end of the data sheet. pin configurations continued at end of data sheet. block diagrams appear at end of data sheet. part pin-package top mark max15024 aatb+t 10 tdfn-ep* atx max15024aatb/v+t 10 tdfn-ep* awt max15024batb+t 10 tdfn-ep* aty max15025 aatb+t 10 tdfn-ep* atz max15025aatb/v+t 10 tdfn-ep* aye max15025batb+t 10 tdfn-ep* aua max15025catb+t 10 tdfn-ep* aub MAX15025DATB+t 10 tdfn-ep* auc
max15024/max15025 single/dual, 16ns, high sink/source current gate drivers 2 _______________________________________________________________________________________ absolute maximum ratings max15024 electrical characteristics (v cc = v drv = v reg = 10v, fb/set = gnd, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = t j = + 25?). (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ............................................................-0.3v to +30v reg to gnd ..............-0.3v to the lower of +22v or (v cc + 0.3v) drv to pgnd .........................................................-0.3v to +22v in_ ..........................................................................-0.3v to +22v fb/set to gnd.........................................................-0.3v to +6v p_out to drv ........................................................-22v to +0.3v n_out to pgnd.....................................................-0.3v to +22v out1, out2 to pgnd ..............................-0.3v to (v drv + 0.3v) pgnd to gnd .......................................................-0.3v to +0.3v p_out, n_out continuous source/sink current* .......... 200ma out1, out2 continuous source/sink current*................200ma continuous power dissipation (t a = +70?) 10-pin tdfn, single-layer board (derate 18.5mw/? above +70?) ...........................1481.5mw 10-pin tdfn, multilayer board (derate 24.4mw/? above +70?) ...........................1951.2mw operating temperature range .........................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units system specifications max15024b 6.5 28.0 v cc powered only, v reg = v drv decoupled with minimum 1? to gnd max15024a 4.5 28.0 v cc = v reg = v drv (max15024b) 6.5 18.0 input voltage range v cc v cc = v reg = v drv (max15024a) 4.5 18.0 v v drv turn-on voltage v drv _ on v cc = v reg = 10v, in+ = v cc , in- = gnd 1.7 2.3 v quiescent supply current in_ = v cc or gnd 700 1350 ? quiescent supply current under uvlo condition in_ = v cc or gnd 250 ? switching supply current switching at 250khz, c l = 0f 1.5 3.0 ma v cc undervoltage lockout uvlo_ v cc v cc rising 3.0 3.4 3.8 v v cc undervoltage-lockout hysteresis 300 mv v cc rising 100 v cc undervoltage lockout to output delay v cc falling 2 ? reg regulator (v cc = 12v, reg = v drv , c l = 1f, fb/set = gnd) output voltage v reg 12v < v cc < 28v, 0 < i load < 10ma 91011 v v cc = 6.5v, i load = 100ma 0.4 0.9 dropout voltage v r _ do v cc = 4.5v, i load = 50ma 0.2 0.5 v load regulation v cc = 12v, i load = 0 to 100ma 1 % line re g ulation 12v < v cc < 28v 10 mv * continuous output current is limited by the power dissipation of the package. note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to http://www.maxim-ic.com/thermal-tutorial . package thermal characteristics (note 1) 10 tdfn junction-to-ambient thermal resistance ( ja )...............41?/w junction-to-case thermal resistance ( jc )......................9?/w
max15024/max15025 single/dual, 16ns, high sink/source current gate drivers _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units driver output (sink) t a = +25? 0.45 0.60 v cc = v reg = v drv = 10v, sinking 100ma t a = +125? 0.625 0.850 t a = +25? 0.50 0.65 driver output resistance r on-n v cc = v reg = v drv = 4.5v, sinking 100ma (max15024a) t a = +125? 0.7 0.9 peak output current i pk-n v n_out = 10v 8 a maximum load capacitance soa condition: c l x v drv 2 20?, for v drv = 10v 200 nf latchup robustness 500 ma driver output (source) t a = +25? 0.875 1.500 v cc = v reg = v drv = 10v, sourcing 100ma t a = +125? 1.2 2.0 t a = +25? 0.95 1.65 driver output resistance r on-p v cc = v reg = v drv = 4.5v, sourcing 100ma (max15024a) t a = +125? 1.25 2.20 peak output current i pk-p v p_out = 0v 4 a latchup robustness 500 ma logic inputs max15024a 2.0 logic 1 input voltage v ih max15024b 4.25 v max15024a 0.8 logic 0 input voltage v il max15024b 2 v max15024a 0.4 logic input hysteresis max15024b 1 v logic input current leakage v in = 18v or v gnd -75 0.01 +75 ? input capacitance 10 pf switching characteristics for v cc = v drv = v reg = 10v, p_out and n_out are connected together (see figure 1) c load = 1nf 3 c load = 5nf 12 rise time t r c load = 10nf 24 ns c load = 1nf 3 c load = 5nf 8 fall time t f c load = 10nf 16 ns turn-on delay time t d-on c load = 1nf (note 3) 8 16 32 ns turn-off delay time t d-off c load = 1nf (note 3) 8 16 32 ns mismatch propagation delays from inverting and noninverting inputs to output c load = 1nf (note 3) -9 1 +9 ns max15024 electrical characteristics (continued) (v cc = v drv = v reg = 10v, fb/set = gnd, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = t j = + 25?). (note 2)
max15024/max15025 single/dual, 16ns, high sink/source current gate drivers 4 _______________________________________________________________________________________ max15024 electrical characteristics (continued) (v cc = v drv = v reg = 10v, fb/set = gnd, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = t j = + 25?). (note 2) parameter symbol conditions min typ max units switching characteristics for v cc = v drv = v reg = 4.5v (see figure 1) (max15024a) c load = 1nf 3 c load = 5nf 11 rise time t r c load = 10nf 22 ns c load = 1nf 2.5 c load = 5nf 8 fall time t f c load = 10nf 16 ns turn-on delay time t d-on c load = 1nf 18 ns turn-off delay time t d-off c load = 1nf 18 ns mismatch propagation delays from inverting and noninverting inputs to output c load = 1nf 2 ns minimum input pulse width that changes the output t pw 15 ns thermal characteristics thermal-shutdown temperature temperature rising +160 ? thermal-shutdown temperature hysteresis 15 ? max15025 electrical characteristics (v cc = v drv = v reg = 10v, fb/set = gnd, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = t j = +25?). (note 2) parameter symbol conditions min typ max units system specifications max15025b/d 6.5 28 v cc powered only, v reg = v drv decoupled with minimum 1? to gnd max15025a/c 4.5 28 v cc = v reg = v drv (max15025b/d) 6.5 18.0 input voltage range v cc v cc = v reg = v drv (max15025a/c) 4.5 18.0 v v drv turn-on voltage v drv _ on v cc = v reg = 10v, in1 = v cc , in2 = v cc (m ax 15025a/b) or gn d for ( m ax 15025c /d ) 1.7 2.3 v quiescent supply current in_ = v cc or gnd 700 1350 ? quiescent supply current under uvlo condition in_ = v cc or gnd 250 ? switching supply current switching at 250khz, c l = 0f 1.5 3.0 ma v cc undervoltage lockout uvlo_ v cc v cc rising 3.0 3.4 3.8 v
max15024/max15025 single/dual, 16ns, high sink/source current gate drivers _______________________________________________________________________________________ 5 max15025 electrical characteristics (continued) (v cc = v drv = v reg = 10v, fb/set = gnd, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = t j = +25?). (note 2) parameter symbol conditions min typ max units v cc undervoltage-lockout hysteresis 300 mv v cc rising 100 v cc undervoltage lockout to output delay v cc falling 2 ? reg regulator (v cc = 12v, v reg = v drv , c l = 1f, fb/set = gnd) output voltage v reg 12v < v cc < 28v, 0 < i load < 10ma 9 10 11 v v cc = 6.5v, i load = 100ma 0.4 0.9 dropout voltage v r _ do v cc = 4.5v, i load = 50ma 0.2 0.5 v load regulation v cc = 12v, i load = 0 to 100ma 1 % line regulation 12v < v cc < 28v 10 mv fb/set reference voltage external resistive divider connected at fb/set 1.10 1.23 1.35 v fb/set threshold v fb rising 220 mv fb/set input leakage current v fb = 4.5v -125 +125 na driver output sink t a = +25? 1.0 1.6 v cc = v reg = v drv = 10v, sinking 100ma t a = +125? 1.25 2.10 t a = +25? 1.10 1.65 driver output resistance r on-n v cc = v reg = v drv = 4.5v, sinking 100ma (max15025a/c) t a = +125? 1.5 2.2 peak output current i pk-n v out_ = 10v 4 a maximum load capacitance soa condition: c l x v drv 2 20?, for v drv = 10v 100 nf latchup robustness 500 ma driver output source t a = +25? 1.75 2.50 v cc = v reg = v drv = 10v, sourcing 100ma t a = +125? 2.25 3.50 t a = +25? 1.85 2.60 driver output resistance r on-p v cc = v reg = v drv = 4.5v, sourcing 100ma (max15025a/c) t a = +125? 2.50 3.75 peak output current i pk-p v out_ = 0v 2 a latchup robustness 500 ma logic inputs max15025a/c 2.0 logic 1 input voltage v ih max15025b/d 4.25 v max15025a/c 0.8 logic 0 input voltage v il max15025b/d 2 v max15025a/c 0.4 logic input hysteresis max15025b/d 1 v logic input current leakage v in = 18v or v gnd -75 +0.01 +75 ? input capacitance 10 pf
max15024/max15025 single/dual, 16ns, high sink/source current gate drivers 6 _______________________________________________________________________________________ max15025 electrical characteristics (continued) (v cc = v drv = v reg = 10v, fb/set = gnd, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = t j = +25?). (note 2) parameter symbol conditions min typ max units switching characteristics for v cc = v drv = v reg = 10v (see figure 1) c load = 1nf 6 c load = 5nf 24 rise time t r c load = 10nf 48 ns c load = 1nf 5 c load = 5nf 16 fall time t f c load = 10nf 32 ns turn-on delay time t d-on c load = 1nf (note 3) 8 16 32 ns turn-off delay time t d-off c load = 1nf (note 3) 8 16 32 ns mismatch propagation delays between 2 channels c load = 1nf (note 3) -9 1 +9 ns switching characteristics for v cc = v drv = v reg = 4.5v (see figure 1) (max15025a/c) c load = 1nf 5 c load = 5nf 20 rise time t r c load = 10nf 42 ns c load = 1nf 4 c load = 5nf 15 fall time t f c load = 10nf 30 ns turn-on delay time t d-on c load = 1nf 18 ns turn-off delay time t d-off c load = 1nf 18 ns mismatch propagation delays between 2 channels c load = 1nf 2 ns minimum input pulse width that changes the output t pw 15 ns thermal characteristics thermal-shutdown temperature temperature rising +160 ? thermal-shutdown temperature hysteresis 15 ? note 2: all devices are 100% production tested at t a = +25?. limits over temperature are guaranteed by design. note 3: design guaranteed by bench characterization. limits are not production tested.
max15024/max15025 single/dual, 16ns, high sink/source current gate drivers _______________________________________________________________________________________ 7 rise time vs. supply voltage (dual driver with 5nf load) max15024/25 toc01 supply voltage (v) rise time (ns) 19 18 17 16 15 14 13 12 11 10 20 30 40 0 10 20 t a = +125 c max15025 t a = +85 c t a = +25 c t a = -40 c t a = 0 c fall time vs. supply voltage (with 5nf load) max15024/25 toc02 supply voltage (v) fall time (ns) 18 16 14 12 15 20 25 30 10 10 20 t a = +125 c t a = +85 c t a = +25 c t a = -40 c t a = 0 c max15025 propagation delay time vs. temperature (1nf load) max15024/25 toc03 temperature ( c) propagation delay time (ns) 120 100 80 60 40 20 0 -20 -40 8 10 12 14 16 18 6 -60 140 rising falling supply current vs. supply voltage (programmed externally to 5v) max15024/25 toc04 supply voltage (v) supply current ( a) 18 16 14 12 10 8 6 4 2 500 1000 1500 2000 2500 0 020 1mhz 500khz 75khz 40khz 100khz supply current vs. load capacitance max15024/25 toc05 load capacitance (nf) supply current (ma) 8000 6000 4000 2000 6 12 18 24 30 0 0 10,000 switching 250khz v cc = v reg = v drv = 10v not switching supply current vs. temperature max15024/25 toc06 temperature ( c) supply current ( a) 80 40 0 200 400 600 800 1000 1200 1400 1600 1800 0 -40 120 switching 250khz not switching v cc = v reg = v drv = 10v input threshold voltage vs. supply voltage (ttl) max15024/25 toc07 supply voltage (v) input threshold voltage (v) 16 12 8 0.5 1.0 1.5 2.0 2.5 3.0 0 420 rising falling supply current vs. logic in max15024/25 toc08 input voltage (v) supply current ( a) 5 4 1 2 3 200 400 600 800 1000 1200 1400 1600 00 06 input high to low input low to high logic input voltage vs. output voltage (5nf rising) max15024/25 toc09 20ns/div in_ 1v/div out_ 5v/div max15025 typical operating characteristics (t a = +25?, unless otherwise noted.)
max15024/max15025 single/dual, 16ns, high sink/source current gate drivers 8 _______________________________________________________________________________________ logic input voltage vs. output voltage (5nf falling) max15024/25 toc10 20ns/div in_ 1v/div out_ 5v/div max15025 logic input voltage vs. output voltage (10nf rising) max15024/25 toc11 20ns/div in_ 1v/div out_ 5v/div max15025 logic input voltage vs. output voltage (10nf falling) max15024/25 toc12 20ns/div in_ 1v/div out_ 5v/div max15025 propagation delay mismatch vs. temperature max15024/25 toc13 temperature ( c) propagation delay between channels (ns) 80 40 0 0.5 1.0 1.5 2.0 2.5 3.0 0 -40 120 line regulation of v reg (programmed externally to 5.04v) max15024/25 toc14 supply voltage v reg (v) 25 20 15 10 4.8 4.9 5.0 5.1 5.2 5.3 4.7 530 load regulation of v reg max15024/25 toc15 load current (ma) v reg (v) 180 160 140 120 100 80 60 40 20 9.5 10.0 10.5 11.0 9.0 0 200 fb/set voltage vs. temperature max15024/25 toc16 temperature ( c) fb/set voltage (v) 100 80 60 40 20 1.232 1.234 1.236 1.238 1.240 1.230 0120 fb/set current vs. temperature max15024/25 toc17 temperature ( c) fb/set current (na) 100 80 60 40 20 5 10 15 20 0 0120 typical operating characteristics (continued) (t a = +25?, unless otherwise noted.)
max15024/max15025 single/dual, 16ns, high sink/source current gate drivers _______________________________________________________________________________________ 9 pin description pin max15024 max15025a max15025b max15025c max15025d name function 1 1 1 fb/set ldo regulator output set. feedback for v reg adjustment (v fb > 200mv). connect fb/set to gnd for a fixed 10v output reg. connect fb/set to a resistor ladder to set v reg . 22 2v cc power-supply input. bypass to gnd with a low-esr ceramic capacitor of 1?. input of the internal housekeeping regulator and of the main reg regulator. 3 3 3 gnd signal ground 4 in+ driver noninverting logic input. connect to v cc when not used. 4 4 in1 driver 1 noninverting logic input 5 in- driver inverting logic input. connect to gnd when not used. 5 in2 driver 2 noninverting logic input 5 in2 driver 2 inverting logic input 6 6 6 pgnd power ground. sink current return. source of the internal pulldown n-channel transistor. 7 n_out sink output. open-drain n-channel output. n_out sinks current for power mosfet turn-off. 7 7 out2 driver 2 output 8 p_out source output. pullup p-channel output (open drain). sources current for power mosfet turn-on. 8 8 out1 driver 1 output 9 9 9 drv output driver supply voltage. decouple drv with a low esr > 0.1? ceramic capacitor to pgnd placed in close proximity to the device. drv can be powered independently from reg. connect drv, reg, and v cc together when there is no need for special drv supply sequencing and the power-mosfet gate voltage does not need to be regulated or limited. 10 10 10 reg voltage regulator output. connect to drv for driving the power mosfet with regulated v gs amplitude. bypass with a low-esr 1? (minimum) ceramic capacitor to gnd placed in close proximity to the device to ensure regulator stability. ep exposed pad. internally connected to gnd. connect to gnd plane or thermal pad and use multiple vias to a solid copper area on the bottom of the pcb.
max15024/max15025 single/dual, 16ns, high sink/source current gate drivers 10 ______________________________________________________________________________________ detailed description the max15024 single gate driver? internal source and sink transistor outputs are brought out of the ic to inde- pendent outputs allowing control of the external mosfet? rise and fall time. the max15024 single gate driver is capable of sinking an 8a peak current and sourcing a 4a peak current. the max15025 dual gate drivers are capable of sinking a 4a peak current and sourcing a 2a peak current. an integrated adjustable low-dropout linear voltage regulator (ldo) provides gate drive amplitude control and optimization. the single gate-driver propagation delay time is minimized and matched between the inverting and noninverting inputs. the dual gate-driver propagation delay is matched between channels. the max15024 has a dual input (in+ and in-), allows the use of an inverting or noninverting input, and is offered in ttl or cmos-logic standards. the max15025 is offered with configurations of inverting and noninverting inputs with ttl or cmos standards (see the selector guide ). ldo voltage regulator feedback control the max15024/max15025 include an internal ldo designed to deliver a stable reference voltage for use as a supply voltage for the internal mosfet gate dri- vers. connect the ldo feedback fb/set to gnd to set v reg to a stable 10v. connect fb/set to a resistor- divider between v reg and gnd to set v reg : v reg = v fb/set x (1 + r2 / r1) (see figure 2) v cc undervoltage lockout when v cc is below the uvlo threshold, the internal n- channel transistor is on and the internal p-channel tran- sistor is off, holding the output at gnd independent of the state of the inputs so that the external mosfets remain off in the uvlo condition. the uvlo threshold is 3.5v (typ) with 200mv (typ) hysteresis to avoid chattering. when the device is operated at very low temperatures and below the uvlo threshold, the driver output could go high impedance. in this case, it is recommended adding a 10k resistor to pgnd to discharge the gate of the external mosfet (see figures 4 and 5). input control the max15024 features inverting and noninverting input terminals. these inputs provide for flexibility of design and use. connect in+ to v cc when using in- as an inverting input. connect in- to gnd when using in+ as a noninverting input. shoot-through protection the max15024/max15025 provide protection that avoids any cross-conduction between the internal p- channel and n-channel devices. it also eliminates shoot- through, thus reducing the quiescent supply current. exposed pad (ep) the max15024/max15025 include an exposed pad allowing greater heat dissipation from the internal die to the outside environment. solder the exposed pad care- fully to gnd or thermal pad to enhance the thermal performance. applications information supply bypassing, device grounding, and placement ample supply bypassing and device grounding are extremely important because when large external capacitive loads are driven, the peak current at the v drv pin can approach 4a, while at the pgnd pin, the peak current can approach 8a. v drv drops and ground shifts are forms of negative feedback for invert- ers and, if excessive, can cause multiple switching when the inverting input is used and the input slew rate is low. the device driving the input should be refer- enced to the max15024/max15025 gnd. ground shifts due to insufficient device grounding can disturb other circuits sharing the same ac ground return path. any series inductance in the v drv , out_, and/or pgnd paths can cause oscillations due to the very high di/dt that results when the max15024/max15025 are switched with any capacitive load. a 0.1? or larger value ceramic capacitor is recommended for bypass- ing v drv to gnd and should be placed as close to the pins as possible. when driving very large loads (> 10nf) at minimum rise time, 10? or more of parallel storage capacitance is recommended. a ground plane is highly recommended to minimize ground return resis- tance and series inductance. care should be taken to place the max15024/max15025 as close as possible to the external mosfet being driven to further minimize board inductance and ac path resistance.
power dissipation power dissipation of the max15024/max15025 con- sists of three components: the quiescent current, capacitive charge and discharge of internal nodes, and the output current (either capacitive or resistive load). the sum of these components must be kept below the maximum power-dissipation limit. the quiescent cur- rent is 700? typ. the current required to charge and discharge the internal nodes is frequency dependent (see the typical operating characteristics ). the max15024/max15025 power dissipation when driving a ground-referenced resistive load is: p = d x r on(max) x i load 2 where d is the fraction of the period the max15024/ max15025s?output pulls high, r on(max) is the maxi- mum on-resistance of the device with the output high (p-channel), and i load is the output load current of the max15024/max15025. for capacitive loads, the power dissipation for each driver is: p = c load x v drv 2 x freq where c load is the capacitive load, v drv is the driver supply voltage, and freq is the switching frequency. layout information the max15024/max15025 mosfet drivers source and sink large currents to create very fast rise and fall edges at the gate of the switching mosfet. the high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. the following printed-circuit board (pcb) layout guidelines are recom- mended when designing with the max15024/max15025: place one or more 1? decoupling ceramic capaci- tor(s) from v drv to pgnd as close to the device as possible. at least one storage capacitor of 10? (min) should be located on the pcb with a low resistance path to the v cc pin of the max15024/max15025. there are two ac current loops formed between the device and the gate of the mosfet being driven. the mosfet looks like a large capacitance from gate to source when the gate is being pulled low. the active current loop is from mosfet gate to out_ of the max15024/max15025 to pgnd of the max15024/max15025, and to the source of the mosfet. when the gate of the mosfet is being pulled high, the active current loop is from the v dd terminal of the v drv terminal of decoupling capaci- tor, to the v drv of the max15024/max15025, to the out_ of the max15024/max15025, to the mosfet gate, to the mosfet source, and to the negative ter- minal of the decoupling capacitor. both charging current loop and discharging current loop are impor- tant. it is important to minimize the physical distance and the impedance in these ac current paths. keep the device as close as possible to the mosfet. in the multilayer pcb, the inner layers should consist of a gnd plane containing the discharging and charging current loops. max15024/max15025 single/dual, 16ns, high sink/source current gate drivers ______________________________________________________________________________________ 11 in+ p_out and n_out connected together or out1/out2 v il v ih t d-off t f 90% 10% t d-on t r figure 1. timing diagram
max15024/max15025 single/dual, 16ns, high sink/source current gate drivers 12 ______________________________________________________________________________________ typical operating circuits max15024 reg r2 r1 v cc (up to 28v) drv fb/set p_out n_out pgnd gnd in- v cc in+ figure 2. use r1, r2 to program v reg < 18v, or. connect fb/set to gnd for v reg = 10v (connect ep to gnd) max15024 v cc c1 v cc (up to 18v) reg fb/set p_out drv v drv < 18v n_out pgnd gnd in- in+ figure 3. operation using a different supply rail for drv (connect ep to gnd) max15024 v cc v cc (up to 18v) reg fb/set p_out drv n_out pgnd gnd in- in+ figure 4. operation using a v cc = drv = reg (connect ep to gnd) max15025 reg r2 r1 v cc (up to 28v) drv fb/set out1 out2 pgnd gnd in1 v cc in2 figure 5. use r1, r2 to program v reg < 18v, or. connect fb/set to gnd for v reg = 10v (connect ep to gnd)
ldo predriver predriver in_ logic level shift-up in_ logic level shift-up uvlo v cc fb/set in+ in- gnd reg drv p_out n_out pgnd n p ldo v cc fb/set in1 in2 gnd reg drv out1 out2 pgnd uvlo predriver predriver predriver predriver in_ logic level shift-up in_ logic level shift-up in_ logic level shift-up in_ logic level shift-up max15025 max15024a max15024b p p n n max15024/max15025 single/dual, 16ns, high sink/source current gate drivers ______________________________________________________________________________________ 13 block diagrams
max15024/max15025 single/dual, 16ns, high sink/source current gate drivers 14 ______________________________________________________________________________________ selector guide part no. of channels peak currents (sink/source) inputs logic levels top mark max15024aatb+ 1 8a/4a complementary ttl atx max15024aatb/v+ 1 8a/4a complementary ttl awt max15024batb+ 1 8a/4a complementary cmos aty max15025aatb+ 2 4a/2a noninverting ttl atz max15025aatb/v+ 2 4a/2a noninverting ttl aye max15025batb+ 2 4a/2a noninverting cmos aua max15025catb+ 2 4a/2a noninverting (1)/ inverting (2) ttl aub MAX15025DATB+ 2 4a/2a noninverting (1)/ inverting (2) cmos auc note: all devices operate in a -40? to +125? temperature range and come in a 10-pin tdfn package. ep top view 10 87 reg out1 out2 fb/set gnd in1 max15025a max15025b 9 drv v cc 6 134 25 pgnd in2 tdfn ep 10 87 reg out1 out2 fb/set gnd in1 max15025c max15025d 9 drv v cc 6 134 25 pgnd in2 tdfn pin configurations (continued)
max15024/max15025 single/dual, 16ns, high sink/source current gate drivers ______________________________________________________________________________________ 15 chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 10 tdfn t1033+1 21-0137 90-0003
max15024/max15025 single/dual, 16ns, high sink/source current gate drivers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 10/07 initial release 1 3/08 released max15024a/max15025b/c/d versions 1?, 9, 13 2 4/10 removed future product (max15024c/d, max15025e-h); minimum and maximum specifications added to the ec table 1?, 9, 10, 12?5 3 4/11 added automotive part numbers to ordering information and selector guide 1, 14

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